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Datasheet V1.2 May 2010
ICB2FL01G
Smart Ballast Control IC for Fluorescent Lamp Ballasts
Published by Infineon Technologies AG
http://www.infineon.com
IFAG IMM API SPI AC TM
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2nd Generation FL-Controller for FL-Ballasts
ICB2FL01G Revision History Datasheet ICB2FL01G Actual Release: V1.2 Date: 05.05.2010 Previous Release: 18.02.2009 Page of Page of Subjects changed since last release actual Rel. prev. Rel. 3 3 Figure 1 Update 9 9 LVS1 Text Update 11 11 Figure 3 Update 21 21 Capter 2.4.2.1 Text Update and Figure 15 Update 24 24 PFC ON Time versus iZCD Signal 29 29 Update of Figure 26 and Text 38 38 Update 3.3 State Diagram 40 40 Update Protection Function Matrix HS Fil. Detection @ LVS1 53 53 BOM Update deleted Partnumbers of MOSFETs 54 54 Figure 42 Schematic of a serial Lamp Ballast Design 54 55 Figure 42 rename in Figure 43 and shift one page
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Published by Infineon Technologies AG 81726 Munich, Germany (c) 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Datasheet
Page 2 from 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
2nd
Generation FL-Controller for Fluorescent Lamp Ballasts
Product Highlights
Lowest Count of external Components 900V-Half-Bridge driver with coreless Transformer Technology Supports Customer In-Circuit Test Mode for reduced Tester Time Supports Multi-Lamp Designs Integrated digital Timers up to 40 seconds Numerous Monitoring and Protection Features for highest Reliability All Parameter are valid over a wide Temperature Range of TJ = - 25C until + 125C Features PFC Discontinuous Mode PFC for Load Range 0 to 100% Integrated digital Compensation of PFC Control Loop Improved Compensation for low THD of AC Input Current also in DCM Operation Adjustable PFC Current Limitation Features Lamp Ballast Inverter Adjustable Detection of Overload and Rectifier Effect (EOL) Detection of Capacitive Load operation Improved Ignition Control allows Operation close to the magnetic Saturation of the lamp Inductors Restart with skipped Preheating at short interruptions of Line Voltage (for Emergency Lighting) Parameters adjustable by Resistors only Pb-free Lead Plating; RoHS compliant
Figure 1: Typical Application Circuit of Ballast for a single Fluorescent Lamp Description The FL-Controller ICB2FL01G is designed to control fluorescent lamp ballast including a discontinuous mode Power Factor Correction (PFC), a lamp inverter control and a high voltage level shift half-bridge driver. The control concept covers requirements for T5 lamp ballasts for single and multi-lamp designs. st ICB2FL01G is based on the 1 Generation FL-Controller Technology, is easy to use and simply to design in. Therefore a basis for a cost effective solution for fluorescent lamp ballasts of high reliability. Figure 1 shows a typical application circuits of ballast for a single fluorescent T8 lamp with current mode preheat. Datasheet Page 3 from 56 ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Table of Contents
1 Pin Configuration and Description............................................................................................... 6 1.1 1.2 2 Pin Configuration....................................................................................................................... 6 Pin Description .......................................................................................................................... 6
Functional Description ................................................................................................................ 11 2.1 Typical Application Circutry..................................................................................................... 11
2.2 Normal Start Up ...................................................................................................................... 12 2.2.1 Operating Levels from UVLO to Soft Start............................................................................ 13 2.2.2 Operating Levels from Soft Start to Run Mode ..................................................................... 15 2.3 Filament Detection during Start Up and Run Mode ................................................................ 17 2.3.1 Start Up with broken Low Side Filament............................................................................... 17 2.3.2 Low Side Filament Detection during Run Mode.................................................................... 18 2.3.3 Start Up with broken High Side Filament .............................................................................. 19 2.4 PFC Pre Converter.................................................................................................................. 20 2.4.1 Discontinuous Conduction and Critical Conduction Mode Operation ................................... 20 2.4.2 PFC Bus Voltage Sensing..................................................................................................... 21 2.4.2.1 Bus Over Voltage and PFC Open Loop ................................................................... 21 2.4.2.2 Bus Voltage 95% and 75% Sensing......................................................................... 21 2.4.3 PFC Structure of Mixed Signal.............................................................................................. 22 2.4.4 THD Correction via ZCD Signal ............................................................................................ 23 2.4.5 Optional THD Correction dedicated for DCM Operation....................................................... 24 2.5 Detection of End-of-Life and Rectifier Effect........................................................................... 25 2.5.1 Detection of End of Life 1 (EOL1) - Lamp Overvoltage........................................................ 25 2.5.2 Detection of End-of-Life (EOL2) - Rectifier Effect ................................................................ 26 2.6 Detection of Capacitive Load .................................................................................................. 27 2.6.1 Capacitive Load 1 (Idling Detection - Current Mode Preheating) ........................................ 28 2.6.2 Capacitive Load 2 (Over Current / Operation below Resonance) ........................................ 28 2.6.3 Adjustable self adapting Dead Time ..................................................................................... 29 2.7 Emergency Lighting ................................................................................................................ 30 2.7.1 Short Term PFC Bus Under Voltage..................................................................................... 31 2.7.2 Long Term PFC Bus Under Voltage ..................................................................................... 32 2.8 Built in Customer Test Mode Operation.................................................................................. 33 2.8.1 Pre Heating Test Mode ......................................................................................................... 33 2.8.1.1 Skip the Pre Heating Phase - Set RTPH Pin to GND.............................................. 33 2.8.1.2 IC remains in Pre Heating Phase ............................................................................. 34 2.8.2 Deactivation of the Filament Detection ................................................................................. 35 2.8.3 Built in Customer Test Mode (Clock Acceleration) ............................................................... 36 2.8.3.1 Enabling of the Clock Acceleration........................................................................... 36 2.8.3.2 Starting the Chip with accelerated Clock.................................................................. 36 3 State Diagram ............................................................................................................................... 37 3.1 3.2 3.3 4 Features during different operating modes ............................................................................. 37 Operating Flow of the Start UP Procedure into the Run Mode............................................... 38 Auto Restart and Latched Fault Condition Mode.................................................................... 39
Protection Functions Matrix........................................................................................................ 40 Page 4 from 56 ICB2FL01G V1.2
Datasheet
2nd Generation FL-Controller for FL-Ballasts
5 Electrical Characteristics ............................................................................................................ 41 5.1 5.2 Absolute Maximum Ratings .................................................................................................... 41 Operating Range..................................................................................................................... 43
5.3 Characteristics ........................................................................................................................ 44 5.3.1 Power Supply Section ........................................................................................................... 44 5.3.2 PFC Section .......................................................................................................................... 45 5.3.2.1 PFC Current Sense (PFCCS)................................................................................... 45 5.3.2.2 PFC Zero Current Detection (PFCZCD)................................................................... 45 5.3.2.3 PFC Bus Voltage Sense (PFCVS) ........................................................................... 45 5.3.2.4 PFC PWM Generation.............................................................................................. 46 5.3.2.5 PFC Gate Drive (PFCGD) ........................................................................................ 46 5.3.2.6 Auxiliary (AUX) ......................................................................................................... 46 5.3.3 Inverter Section ..................................................................................................................... 47 5.3.3.1 Low Side Current Sense (LSCS).............................................................................. 47 5.3.3.2 Low Side Gate Drive (LSGD) ................................................................................... 48 5.3.3.3 Inverter Control Run (RFRUN) ................................................................................. 49 5.3.3.4 Inverter Control Preheating (RFPH, RTPH) ............................................................. 49 5.3.3.5 Restart after Lamp Removal (RES).......................................................................... 50 5.3.3.6 Lamp Voltage Sense (LVS1, LVS2) ......................................................................... 50 5.3.3.7 High Side Gate Drive (HSGD) .................................................................................. 51 5.3.3.8 Timer Section ........................................................................................................... 51 5.3.3.9 Built in Customer Test Mode .................................................................................... 51 6 Application Example .................................................................................................................... 52 6.1 6.2 6.3 7 Schematic Ballast 54W T5 Single Lamp................................................................................. 52 Bill of Material.......................................................................................................................... 53 Multi Lamp Ballast Topologies ................................................................................................ 54
Package Outlines ......................................................................................................................... 56
Datasheet
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ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
1
1.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 HSGND HSVCC HSGD
Pin Configuration and Description
Pin Configuration
Function Low side current sense (inverter) Low side Gate drive (inverter) Supply voltage Low side Ground PFC Gate drive PFC current sense PFC voltage sense Set R for run frequency Set R for preheat frequency Set R for preheating time Restart after lamp removal Lamp voltage sense 1 Lamp voltage sense 2 Auxiliary output Creepage distance High side ground High side supply voltage High side Gate drive (inverter) Not connected LSCS LSGD VCC GND PFCGD PFCCS PFCVS RFRUN RFPH RTPH RES LVS1 LVS2 AUX
1.2
Pin Description
Pin Symbol
PFCZCD PFC zero current detector
Figure 2: Package PG-DSO-19-1
LSCS (Low-side current sense, Pin 1) This pin is directly connected to the shunt resistor which is located between the Source terminal of the low-side MOSFET of the inverter and ground. Internal clamping structures and filtering measures allow for sensing the Source current of the low side inverter MOSFET without additional filter components. There is a first threshold of 0.8V. If this threshold is exceeded for longer than 500ns during preheat or run mode, an inverter over current is detected and causes a latched shut down of the IC. The ignition control is activated if the sensed slope at the LSCS pin reaches typically 205 mV/s 25 mV/s and exceeds the 0.8V threshold. This stops the decreasing of the frequency and waits for ignition. The ignition control is now continuously monitored by the LSCS PIN. The Ignition control is designed to handle a choke operation in saturation while ignition in order to reduce the choke size. If the sensed current signal exceeds a second threshold of 1.6V for longer than 500ns during start-up, soft start, ignition mode and pre-run, the IC changes over into a latched shut down. There are further thresholds active at this pin during run mode that detects a capacitive mode operation. A first threshold at 100mV needs to sense a positive current during the second 50% on-time of the low-side MOSFET for proper operation (Capload 1). A second threshold of 100mV senses the current before the high-side MOSFET is turned on. A voltage level below of this threshold indicates a faulty operation (Capload 2). Finally a third threshold at 2.0 V senses even short overcurrent during turn-on of the high-side MOSFET such as they are typical for reverse recovery currents of a diode (Capload 2). If one of these three comparator thresholds indicate wrong operating conditions for longer than 620s (Capload 2) or 2500ms (Capload 1) in run mode, the IC turns off the Gates and changes into fault mode due to detected capacitive mode operation (non-zero voltage switching). The threshold of -100mV is also used to adjust the dead time between turn-off and turn-on of the half-bridge drivers in a range of 1.25s to 2.5s during all operating modes.
Datasheet
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ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
LSGD (Low-side Gate drive, Pin 2) The Gate of the low-side MOSFET in a halfbridge inverter topology is controlled by this pin. There is an active L-level during UVLO (under voltage lockout) and a limitation of the max Hlevel at 11.0 V during normal operation. In order to turn-on the MOSFET softly (with a reduced diDRAIN/dt); the Gate voltage rises within 220ns typically from L-level to H-level. The fall time of the Gate voltage is less than 50ns in order to turn off quickly. This measure produces different switching speeds during turn-on and turn-off as it is usually achieved with a diode parallel to a resistor in the Gate drive loop. It is recommended to use a resistor of typically 10 between drive pin and Gate in order to avoid oscillations and in order to shift the power dissipation of discharging the Gate capacitance into this resistor. The dead time between LSGD signal and HSGD signal is self adapting between 1.25s and 2.5s. Vcc (Supply voltage, Pin 3) This pin provides the power supply of the ground related section of the IC. There is a turn-on threshold at 14.1V and an UVLO threshold at 10.6V. Upper supply voltage level is 17.5V. There is an internal zener diode clamping VCC at 16.3V (at IVCC=2mA typically). The maximum zener current is internally limited to 5mA. For higher current levels an external zener diode is required. Current consumption during UVLO and during fault mode is less than 170A. A ceramic capacitor close to the supply and GND pin is required in order to act as a low-impedance power source for Gate drive and logic signal currents. In order to use a skipped preheating after short interruptions of mains supply it is necessary to feed the start-up current (160A) from the bus voltage. Note: for external VCC supply see notes in flowchart chapter 3.3. GND (Ground, Pin 4) This pin is connected to ground and represents the ground level of the IC for supply voltage, Gate drive and sense signals. PFCGD (PFC Gate drive, Pin 5) The Gate of the MOSFET in the PFC preconverter designed in boost topology is controlled by this pin. There is an active L-level during UVLO and a limitation of the max H-level at 11.0 V during normal operation. In order to turn-on the MOSFET softly (with a reduced diDRAIN/dt), the Gate drive voltage rises within 220ns from L-level to H-level. The fall time of the Gate voltage is less than 50ns in order to turn off quickly. A resistor of typically 10 between drive pin and Gate in order to avoid oscillations and in order to shift the power dissipation of discharging the Gate capacitance into this resistor is recommended. The PFC section of the IC controls a boost converter as a PFC preconverter in discontinuous conduction mode (DCM). Typically the control starts with Gate drive pulses with a fixed on-time of typically 4.0s at VACIN = 230V increasing up to 22.7s and with an off-time of 47s. As soon as sufficient zero current detector (ZCD) signals are available, the operation mode changes from a fixed frequent operation to an operation with variable frequency. The PFC works in a critical conduction mode operation (CritCM) when rated and / or medium load conditions are present. That means triangular shaped currents in the boost converter choke without gaps and variable operating frequency. During low load (detected by an internal compensator) we get an operation with discontinuous conduction mode (DCM) that means triangular shaped currents in the boost converter choke with gaps when reaching the zero current level and variable operating frequency in order to avoid steps in the consumed line current. PFCCS (PFC current sense, Pin 6) The voltage drop across a shunt resistor located between Source of the PFC MOSFET and GND is sensed with this pin. If the level exceeds a threshold of 1.0 V for longer than 200ns the PFC Gate drive is turned off as long as the zero current detector (ZCD) enables a new cycle. If there is no ZCD signal available within 52s after turn-off of the PFC Gate drive, a new cycle is initiated from an internal start-up timer. PFCZCD (PFC zero current detector, Pin 7) This pin senses the point of time when the current through boost inductor becomes zero during off-time of the PFC MOSFET in order to initiate a new cycle. The moment of interest appears when the voltage of the separate ZCD winding changes from positive to negative level which represents a voltage of zero at the inductor windings and therefore the end of current flow from lower input voltage level to higher output voltage level. There is a threshold with hysteresis, for increasing level 1.5V, for decreasing level 0.5V, which detects the change of inductor voltage.
Datasheet
Page 7 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
A resistor, connected between ZCD winding and PIN 7, limits the sink and source current of the sense pin when the voltage of the ZCD winding exceeds the internal clamping levels (6.3V and -2.9V typically @ 5mA) of the IC. If the sensed voltage level of the ZCD winding is not sufficient (e.g. during start-up), an internal start-up timer will initiate a new cycle every 52s after turn-off of the PFC Gate drive. The source current out of this pin during the on-time of the PFC-MOSFET indicates the voltage level of the AC supply voltage. During low input voltage levels the on-time of the PFC-MOSFET is enlarged in order to minimize gaps in the line current during zero crossing of the line voltage and improve the THD (Total Harmonic Distortion) of the line current. An optimization of the THD is possible by trimming of the resistor between this pin and the ZCD-winding. RFRUN (Set R for run frequency, Pin 9) A resistor from this pin to ground sets the operating frequency of the inverter during run mode. Typical run frequency range is 20 kHz to 120 kHz. The set resistor R_RFRUN can be calculated based on the run frequency fRUN according to the equation:
RFRUN =
5 108 Hz f RUN
PFCVS (PFC voltage sense, Pin 8) The intermediate circuit voltage (bus voltage) at the smoothing capacitor is sensed by a resistive RRFRUN RRFPH = divider at this pin. The internal reference f PH RRFRUN voltage for rated bus voltage is 2.5V. There are -1 further thresholds at 0.3125V (12.5% of rated 5 108 Hz bus voltage) for the detection of open control loop and at 1.875V (75% of rated bus voltage) RTPH (Set R for preheating time, Pin 11) for the detection of an under voltage and at A resistor from this pin to ground sets the 2.725V (109% of rated bus voltage) for the preheating time of the inverter during preheat detection of an overvoltage. The overvoltage mode. A set resistor range from zero to 25k threshold operates with a hysteresis of 100mV corresponds to a range of preheating time from (4% of rated bus voltage). For the detection of a zero to 2500ms subdivided in 127 steps. successful start-up the bus voltage is sensed at t Pr eHeating 95% (2.375V). It is recommended to use a RRTPH = ms small capacitor between this pin and GND as a 100 spike suppression filter. k In run mode, a PFC overvoltage stops the PFC Gate drive within 5s. As soon as the bus RES (Restart, Pin 12) voltage is less than 105% of rated level, the A source current out of this pin via resistor and Gate drives are enabled again. If the filament to ground monitors the existence of the overvoltage lasts for longer than 625ms, an low-side filament of the fluorescent lamp for inverter overvoltage is detected and turns off restart after lamp removal. A capacitor from this the inverter the gate drives also. This causes a pin directly to ground eliminates a power down and a power up when VBUS<109%. superimposed AC voltage that is generated as A bus under- (VBUS>75%) or inverter a voltage drop across the low-side filament. overvoltage during run mode is handled as fault With a second sense resistor the filament of a U. In this situation the IC changes into power paralleled lamp can be included into the lamp down mode and generates a delay of 100ms by removal sense. Note: during start up, the chip an internal timer. Then start-up conditions are supply voltage Vcc has to be below 14.1V checked and if valid, a further start-up is before VRES reaches the filament detection initiated. If start-up conditions are not valid, a level. further delay of 100ms is generated. This procedure is repeated maximum seven times. If a start-up is successful within these seven cycles, the situation is interpreted as a short interruption of mains supply and the preheating is skipped. Any further start-up attempt is initiated including the preheating. Datasheet Page 8 of 56 ICB2FL01G V1.2
RFPH (Set R for preheat frequency, Pin 10) A resistor from this pin to ground sets together with the resistor at pin 9 the operating frequency of the inverter during preheat mode. Typical preheat frequency range is run frequency (as a minimum) to 150 kHz. The set resistor R_RFPH can be calculated based on the preheat frequency fPH and the resistor RRFRUN according to the equation:
2nd Generation FL-Controller for FL-Ballasts
During typical start-up with connected filaments of the lamp a current source IRES3 (-21.3 A) is active as long as VCC > 10.6V and VRES < VRES1 (1.6V). An open low-side filament is detected, when VRES > VRES1. Such a condition will prevent the start-up of the IC. In addition the comparator threshold is set to VRES2 (1.3V) and the current source changes to IRES4 (-17.7 A). Now the system is waiting for a voltage level lower than VRES2 at the RES pin that indicates a connected low-side filament, which will enable the start-up of the IC. An open high-side filament is detected when there is no sink current ILVSSINK (>18 A) into both of the LVS pins before the VCC Start-up threshold is reached. Under these conditions the current source at the RES pin is IRES1 (42.6A) as long as VCC > 10.6V and VRES < VRES1 (1.6V) and the current source is IRES2 (35.4 A) when the threshold has changed to VRES2 (1.3V). In this way the detection of the high-side filament is mirrored to the levels on the RES pin. There is a further threshold of 3.2V active at the RES pin during run mode. If the voltage level rises above this threshold for longer than 620s, the IC changes over into latched fault mode. In any case of fault detection with different reaction times the IC turns-off the Gate drives and changes into power down mode with a current consumption of 170A max. An internal timer generates a delay time of 200ms, before start-up conditions are checked again. As soon as start-up conditions are valid, a second startup attempt is initiated. If this second attempt fails, the IC remains in latched fault mode until a reset is generated by UVLO or lamp removal. The RES PIN can be deactivated via set the PIN to GND (durable). LVS1 (Lamp voltage sense 1, Pin 13) Before start-up this pin senses a current fed from the rectified line voltage via resistors through the high-side filaments of the lamp for the detection of an inserted lamp. The sensed current fed into the LVS pin has to exceed 12 A typically at a voltage level of 6.0 V at the LVS pin. The reaction on the high side filament detection is mirrored to the RES pin (see pin 12). In addition the detection of available mains supply after an interruption is sensed by this pin. Together with pin LVS2 and pin RES the IC can monitor the lamp removal of totally four lamps. If the functionality of this pin is not required, e.g. for single lamp designs, it can be disabled by connecting this pin to ground. Datasheet During run mode the lamp voltage is monitored with this pin by sensing a current proportional to the lamp voltage via resistors. An overload is indicated by an excessive lamp voltage. If the peak to peak lamp voltage effects a peak to peak current above a threshold of 21.3APP for longer than 620s, a fault EOL1 (end-of-life) is assumed. If the DC current at the LVS pin exceeds a threshold of 42A for longer than 2500ms, a fault EOL2 (rectifier effect) is assumed. The levels of AC sense current and DC sense current can be set separately by external RC network. Note, in case of a deactivation of the LVS1/2 PIN, a reactivation starts, when the current out the LVS1/2 PIN exceeds VLVSEnable1 in RUN Mode. LVS2 (Lamp voltage sense 2, Pin 14) LVS2 has the same functionality as pin LVS1 for monitoring in parallel an additional lamp circuitry. AUX (Auxiliary output, Pin 15) This pin provides a control current for a NPN bipolar transistor during DCM operating mode of the PFC section. There is a source current of -450A plus the current which is fed into pin PFCZCD from the detector winding available only during the enlarged off-time. That differ the discontinuous conduction mode (DCM) from the critical conduction mode (CritCM). With this transistor a resistor for damping oscillations can be switched to the ZCD winding in order to minimize the line current harmonics during DCM operating mode. If this function is not used, this pin has to be not connected. Pin 16 Not Existing PIN 16 does not exist, in order to provide a wider creepage distance to the high-side gate driver. Please pay attention to relevant standards. HSGND (High-side ground, Pin 17) This pin is connected to the Source terminal of the high-side MOSFET which is also the node of high-side and low-side MOSFET. This pin represents the floating ground level of the highside driver and the high-side supply.
Page 9 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
HSVCC (High-side supply voltage, Pin 18) This pin provides the power supply of the highside ground related section of the IC. An external capacitor between pin 17 and pin 18 acts like a floating battery which has to be recharged cycle by cycle via high voltage diode from low-side supply voltage during on-time of the low-side MOSFET. There is an UVLO threshold with hysteresis that enables high-side section at 10.1V and disables it at 8.4V. HSGD (High-side Gate drive, Pin 19) The Gate of the high-side MOSFET in a halfbridge inverter topology is controlled by this pin. There is an active L-level during UVLO and a limitation of the max H-level at 11.0 V during normal operation. The switching characteristics are the same as described for LSGD (pin 2). It is recommended to use a resistor of about 10 between drive pin and Gate in order to avoid oscillations and in order to shift the power dissipation of discharging the Gate capacitance into this resistor. The dead time between LSGD signal and HSGD signal is self adapting between 1.25s and 2.5s (typically). Not connected (Pin 20) This pin is internally not connected.
Datasheet
Page 10 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2
2.1
Functional Description
Typical Application Circutry
Figure 3: Application Circuit of Ballast for a single Fluorescent Lamp (FL) The schematic in Figure 3 shows a typical application for a T5 single fluorescence lamp. It is designed for universal input voltage from 90 VAC until 270 VAC. The following chapters are explaining the components and referring to this schematic.
Datasheet
Page 11 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.2
Normal Start Up
This chapter describes the basic operation flow (8 phases) from the UVLO (Under Voltage Lock Out) into Run Mode without any error detection. For detailed infromation see the following chapters 2.2.1 and 2.2.2. Figure 4 shows the 8 different phases during a typical start form UVLO (phase 1 Figure 4) to Run Mode (phase 8 Figure 4) into normal Operation (no failure detected). In case the AC line input is switched ON, the VCC voltage rises to the UVLO threshold VCC = 10.6 V (no IC activities during UVLO). If VCC exceeds the first threshold of VCC = 10.6 V, the IC starts the first level of detection activity, the high and low side filament detection during the Start Up Hysteresis (phase 2 Figure 4).
Frequency / Lamp Voltage
135 kHz 100 kHz 50 kHz 42 kHz
1 2 3 4
Frequency
5 6 7 8
60ms 0 kHz
35ms
80ms
11ms
Lamp Voltage 0 - 2500ms
40 - 237ms
625ms
Rated BUS Voltage VBUS
100 % 95 % Rated BUS Voltage
Mode / Time
30 %
Mode / Time Chip Supply Voltage VCC
VCC = 17.5 V VCC = 14.1 V Chip Supply Voltage
VCC = 10.6 V
VCC = 0 V
UVLO
Monitoring
Start Up Soft Start
Preheating
Ignition
Pre-Run
Mode / Time Run Mode into normal Operation
Figure 4: Typical Start Up Procedure in Run Mode (in normal Operation) Followed by the end of the Start Up Hysteresis (phase 2 Figure 4) VCC > 14.1 V and before phase 3 is active, a second level of detection activity senses for 80 s (propagation delay of the IC) whether the rated bus voltage is below 12.5 % or above 105 %. If the previous bus voltage conditions are fulfilled and the filaments are detected, the IC starts the operation with an internally fixed startup frequency of typically 135 kHz (all gates are active). In case the bus voltage reaches a level of 95% of the rated bus voltage within latest 80ms (phase 3 Figure 4), the IC enters the Soft Start. During the Soft Start (phase 4 Figure 4), the Start Up frequency shifts from 135 kHz down to the set preheating frequency (chapter 2.2.2). In the Soft Start phase, the lamp voltage rises and the chip supply voltage reaches its working level from 10.6 V < VCC < 17.5 V. After finish the Soft Start, the IC enters the Preheating mode (phase 5 Figure 4) for preheating the filaments (adjustable time) in order to extend the life cycle of the FL filaments. By finishing the preheating, the controller starts the Ignition (phase 6 Figure 4). During the Ignition phase, the frequency decreases from the set preheating frequency down to the set operation frequency (adjustable see chapter 2.2.2). If the Ignition is successful, the IC enters the Pre - Run mode (phase 7 Figure 4).
Datasheet
Page 12 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
This mode is in order to prevent a malfunction of the IC due to an instable system e.g. the lamp parameters are not in a steady state condition. After finish the 625 ms Pre Run phase, the IC switches over to the Run mode (phase 8 Figure 4) with a complete monitoring.
2.2.1 Operating Levels from UVLO to Soft Start
This chapter describes the operating flow from phase 1 (UVLO) until phase 4 (Soft Start) in detail. The control of the ballast is able to start the operation within less than 100 ms (IC in active Mode). This is achieved by a small Start Up capacitor (about 1F C12 and C13 - fed by start up resistors R11 and R12 in Figure 3) and the low current consumption during the UVLO (IVCC = 130 A - phase 1 Figure 5) and Start Up Hysteresis (IVCC = 160 A - defines the start up resistors - phase 2 Figure 5) phases. The chip supply stage of the IC is protected against over voltage via an internal Zener clamping network which clamps the voltage at 16.3 V and allows a current of 2.5 mA. For clamping currents 1 above 2.5 mA, an external Zener diode (D9 Figure 3) is required.
Figure 5: Progress of Level during a typical Start - UP
1
IGate depends on MOSFET Page 13 of 56 ICB2FL01G V1.2
Datasheet
2nd Generation FL-Controller for FL-Ballasts
Functional Description
In case of VCC exceeds the 10.6 V level and stays below 14.1 V (Start up Hysteresis - phase 2 Figure 5), the IC checks whether the lamps are assembled by detecting a current across the filaments. The low side filaments are checked from a source current of typical IRES3 = - 21.3 A out of PIN 12 RES (Figure 5 IRES). This current produces a voltage drop of VRES < 1.6 V (filament is ok) at the low side filament sense resistor (R 36 in Figure 3), connected to GND (via low side filament). An open low side filament is detected (see chapter 2.3.2), when the voltage at the RES PIN exceeds the VRES > 1.6V threshold (Figure 5 VRES). The high side filaments are checked by a current of ILVS > 12 A typically via resistors R41, R42 and R43 (Figure 3) into the LVS1 PIN 13 (for a single lamp operation) and LVS2 PIN 14 for a multi lamp operation. Note: in case of a single lamp operation, the unused LVS PIN has to be disabled via connection to GND. An open high side filament is detected (see 2.3.3) when there is no sink current into the LVS PIN. This causes a higher source current out of the RES PIN (typical 42.6 A / 35.4 A) in order to exceed VRES > 1.6 V. In case of defect filaments, the IC keeps monitoring until there is an adequate current from the RES or the LVS PIN present (e.g. in case of removal a defect lamp). When VCC exceeds the 14.1 V threshold - by the end of the start up hysteresis in phase 2 Figure 5 the IC waits for 80s and senses the bus voltage. When the rated bus voltage is in the corridor of 12.5% < VBUSrated < 105% the IC powers up the system and enters phase 3 (Figure 5 VBUSrated > 95 % sensing) when not, the IC initiates an UVLO when the chip supply voltage is below VCC < 10.6 V. As soon as the condition for a power up is fulfilled, the IC starts the inverter gate operation with an internal fixed Start Up frequency of 135 kHz. The PFC gate drive starts with a delay of app. 300s. Now, the bus voltage will be checked for a rated level above 95 % for a duration of 80 ms (phase 3 Figure 5). When leaving phase 3, the IC enters the Soft Start phase and shifts the frequency from the internal fixed Start Up frequency of 135 kHz down to the set Preheating frequency e.g. fRFPH = 100 kHz.
Datasheet
Page 14 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.2.2 Operating Levels from Soft Start to Run Mode
This chapter describes the operating flow from phase 5 (Preheating mode) until phase 8 (Run mode) in detail. In order to extend the life time of the filaments, the controller enters - after the Soft Start Phase - the Preheating mode (phase 5 Figure 6). The preheating frequency is set by resistors R22 PIN RFPH to GND in combination with R21 (Figure 3) typ. 100 kHz e.g. R22 = 8.2 k in parallel to R21 = 11.0 k see Figure 3 at theRFRUN - PIN). The preheating time can be selected by the programming resistor (R23 in Figure 3) at PIN RTPH from 0 ms up to 2500 ms (phase 5 Figure 6).
Figure 6: Typical Variation of Operating Frequency during Start Up During Ignition (phase 6 Figure 6), the operating frequency of the inverter is shifted downward in ttyp = 40 ms (tmax = 237 ms) to the run frequency set by a resistor (R21 in Figure 3) at PIN RFRUN to GND (typical 45 kHz with 11.0 k resistor). During this frequency shifting, the voltage and current in the resonant circuit will rise when the operation is close to the resonant frequency with increasing voltage across the lamp. The ignition control is activated if the sensed slope at the LSCS pin reaches typically 205 mV/s 25 mV/s and exceeds the 0.8V threshold. This stops the decreasing of the frequency and waits for ignition. The ignition control is now continuously monitored by the LSCS PIN. The maximum duration of the Ignition procedure is limited to 237 ms. Is there no Ignition within this time frame, the ignition control is disabled and the IC changes over into the latched fault mode. Furthermore, in order to reduce the lamp choke, the ignition control is designed to operate with a lamp choke in magnetic saturation during ignition. For an operation in magnetic saturation during ignition; the voltage at the shunt at the LSCS pin 1 has to be VLSCS = 0.75V when ingition voltage is reached. If the ignition is successful, the IC enters the Pre - Run mode (phase 7 Figure 6). The Pre Run mode is a safety mode in order to prevent a malfunction of the IC due to an instable system e.g. the lamp parameters are not in a steady state condition. After 625 ms Pre Run mode, the IC changes into the Run Mode (phase 8 Figure 6). The Run mode monitors the complete system regarding bus over- and under voltage, open loop, over current of PFC and / or Inverter, lamp over voltage (EOL1) and rectifier effect (EOL2) see chapter 2.5) and capacitive load 1 and 2 (see chapter 2.6).
Datasheet
Page 15 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
Figure 7 shows the lamp voltage versus the frequency during the different phases from Preheating to the Run Mode. The lamp voltage rises by the end of the Preheating phase with a decreasing frequency (e.g. 100 kHz to 50 kHz) up to 700 V during Ignition. After Ignition, the lamp voltage drops down to its working level with continuo decreasing the frequency (Figure 7) down to its working level e.g. 45 kHz (set by a resistor at the RFRUN pin to ground). After stops the decreasing of the frequency, the IC enters the Pre Run mode.
Lamp Voltage vs Frequency @ different Modes
1000 900 800 Lamp Voltage [V] 700 600 500 400 300 200 100 0 10000 Frequency [Hz]
After Ignition Before Ignition
1000 900 800 700 600 500 400 300 200 100 0 100000
Figure 7: Lamp Voltage versus Frequency during the different Start up Phases
Datasheet
Page 16 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.3
Filament Detection during Start Up and Run Mode
The low and high side filament detection is sensed via the RES and the LVS pins. The low side filament detection during start up and run mode is detected via the RES pin only. An open high side filament during start up will be sensed via the LVS and the RES pins.
2.3.1 Start Up with broken Low Side Filament
A source current of IRES3 = - 21.3 A out of the RES pin (12) monitors during a start up (also in Run mode) the existence of a low side filament. In case of an open low side filament during the start up hysteresis (10.6V < VCC < 14.1V) a capacitor (C19 in Figure 3) will be charged up via IRES3 = - 21.3 A. When the voltage at the RES pin (12) exceeds VRES1 = 1.6 V, the controller prevents a power up and clamps the RES voltage internally at VRES = 5.0 V. The gate drives of the PFC and inverter stage do not start working.
Figure 8: Startup with open Low Side Filament
Figure 9: Restart from open Low Side Filament
The IC comparators are set now to a threshold of VRES1 = 1.3V and to IRES4 = - 17.7A, the controller waits until the voltage at the RES pin drops below VRES1 = 1.3V.When a filament is present (Figure 9 section 2), the voltage drops below 1.3V and the value of the source current out of the RES pin is set from IRES4 = - 17.7 A up to IRES3 = - 21.3 A. Now the controller powers up the system including Soft Start and Preheating into the Run mode.
Datasheet
Page 17 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.3.2 Low Side Filament Detection during Run Mode
In case of an open low side filament during Run mode, the current out of the RES pin IRES3 = - 21.3 A charges up the capacitor C19 in Figure 3. If the voltage at the RES pin exceeds the VRES3 = 3.2V threshold, the controller detects an open low side filament and stops the gate drives after a delay of t = 620s of an internal timer.
Figure 10: Open Low Side Filament Run Mode
Figure 11: Restart from open LS Filament
A restart is initiated when a filament is detected e.g. in case of a lamp removal. In case of a filament is present (Figure 11 section 2), the voltage drops below 1.3V and the value of the source current out of the RES pin is set from IRES4 = - 17.7 A up to IRES3 = - 21.3 A. The controller powers up the system including Soft Start and Preheating into the Run mode (Figure 11 section 3).
Datasheet
Page 18 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.3.3 Start Up with broken High Side Filament
An open high side filament during the start up hysteresis (10.6V < VCC < 14.1V) is detected, when the current into the LVS pin 13 or 14 is below ILVS = 12 A (typically). In that case, the current out of the RES pin 12 rises up to IRES1 = - 42.6 A. That causes a voltage at the RES pin crosses VRES1 = 1.6V. The source current is now set to IRES2 = - 35.4 A and another threshold of VRES2 = 1.3V is active. The controller prevents a power up (see Figure 12), the gate drives of the PFC and inverter stage do not start working.
VCC
17.5 V 16.0 V 14.1 V
Start UP with OPEN HIGH Side Filament
Chip Supply Voltage
VCC
17.5 V 16.0 V 14.1 V 10.6 V
Restart from open HIGH Side Filament
Chip Supply Voltage
10.6 V
VRES UVLO Start Up Hysteresis
2.0 V 1.6 V 1.3 V
Time
VRES
2.0 V 1.6 V 1.3 V
Time No Power Up Power UP (into RUN Mode)
No Power UP Time
IRES
42.6A 35.4A 21.3A 17.7A
IRES
42.6A 35.4A 21.3A 17.7A
Time IRES
IRES
ILVS
12A
Time
ILVS
12A
Time ILVS
ILVS VLamp
Time
VLamp
Time
Time
Time
Figure 12: Start Up with open high Side Filament
Figure 13: Restart from open high Side Filament
When the high side filament is present, e.g. insert a lamp, the current of the active LVS pins exceeds ILVS > 12 A (typically), the res current drops from IRES2 = - 35.4 A down to IRES4 = - 17.7 A (Figure 13). Now the controller senses the low side filament. When a low side filament is also present, and the controller drops (after a short delay due to a capacitor at the res pin) below VRES2 = 1.3V, the res current is set to IRES3 = - 21.3 A, the controller powers up the system.
Datasheet
Page 19 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.4
PFC Pre Converter
2.4.1 Discontinuous Conduction and Critical Conduction Mode Operation
The digital controlled PFC pre converter starts with an internally fixed ON time of typical tON = 4.0s and variable frequency. The ON - time is enlarged every 280 s (typical) up to a maximum ON - time of 22.7 s. The control switches quite immediately from the discontinuous conduction mode (DCM) over into critical conduction mode (CritCM) as soon as a sufficient ZCD signal is available. The frequency range in CritCM is 22 kHz until 500 kHz, depending on the power (Figure 14) with a variation of the ON time from 22.7 s > tON > 0.5s.
Discontinuous Conduction Mode (DCM) <> Critical Condution Mode (CritCM)
1000,00 100,00
PFC Frequency [kHz] 50% Duty Cycle
100,00
10,00 10,00 PFC - ON Time [s] 1,00 0,10
0,10 1,00 10,00 100,00
1,00
0,10
0,01
0,01
Normalized Output Power [% ]
Frequency DCM Frequency CritCM Ton DCM Ton CritCM
Figure 14: Operating Frequency and ON Time versus Power in DCM and CritCM Operation For lower loads (POUTNorm < 8 % from the normalized load ) the control operates in discontinuous conduction mode (DCM) with an ON - time from 4.0s and increasing OFF - time. The frequency during DCM is variable in a range from 144 kHz down to typically 22 kHz @ 0.1 % Load (Figure 14). With this control method, the PFC converter enables a stable operation from 100 % load down to 0.1 %. Figure 14 shows the ON time range in DCM and CritCM (Critical Conduction Mode) operation. In the overlapping area of CritCM and DCM is a hysteresis of the ON time which causes a negligible frequency change.
2
2
Normalized Power @ Low Line Input Voltage and maximum Load Page 20 of 56 ICB2FL01G V1.2
Datasheet
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.4.2 PFC Bus Voltage Sensing
Over voltage, open loop, bus 95 % and under voltage states (Figure 15) of the PFC bus voltage are sensed at the PFCVS pin via the network R14, R15, R20 and C11 Figure 3 (C11 acts as a spike suppression filter).
2.4.2.1
Bus Over Voltage and PFC Open Loop
The bus voltage loop control is completely integrated (Figure 16) and provided by an 8 Bit sigma - delta A/D - converter with a typical sampling rate of 280 s and a resolution of 4 mV/Bit. After leaving phase 2 (monitoring), the IC starts the power up (VCC > 14.1V). After power up, the IC senses for 80s - 130s the bus voltage below 12.5% (open loop) or above 105% (bus over voltage). In case of a bus over voltage (VBUSrated > 109 %) or open loop (VBUSrated < 12.5 %) in phases 3 until 8 the IC shuts off the gate drives of the PFC within 5s respective in 1s. In this case, the PFC restarts automatically when the bus voltage is within the corridor (12.5% < VBUSrated < 105 %) again. Is the bus voltage after the 80s - 130s valid, the bus voltage sensing is set to 12.5% < VBUSrated < 109 %. In case leaving these thresholds for longer than 1 (open loop) or 5s (overvoltage) the PFC gate drive stops working until the voltage drops below 105% or exceeds the 12.5% level. If the bus over voltage (> 109%) lasts for longer than 625ms in run mode, the inverter gates also shut off and a power down with complete restart is attempt (Figure 15).
Figure 15: PFC Bus Voltage Operating Level and Error Detection
2.4.2.2
Bus Voltage 95% and 75% Sensing
When the rated bus voltage is in the corridor of 12.5% < VBUSrated < 109 %, the IC will check whether the bus voltage exceeds the 95 % threshold (Figure 15 phase 3) within 80 ms before entering the soft start phase 4. Another threshold is activated when the IC enters the run mode (phase 8). When the rated bus voltage drops below 75% for longer than 84 s, a power down with a complete restart is attempted when a counter exceeds 800 ms. In case of a short term bus under voltage (the bus voltage reaches its working level in run mode before exceeding typically 800 ms (min. 500ms) the IC skips phases 1 until 5 and starts with ignition (condition for emergency lighting see 2.7.1). The internal reference level of the bus voltage sense VPFCVS is 2.5 V (100 % of the rated bus voltage) with a high accuracy. A surge protection is activated in case of a rated bus voltage of VBUS > 109% and a low side current sense voltage of VLSCS > 0.8V for longer as 500ns in PRE RUN and RUN Mode.
Datasheet
Page 21 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.4.3 PFC Structure of Mixed Signal
A digital NOTCH filter eliminates the input voltage ripple - independent from the mains frequency. A subsequent error amplifier with PI characteristic cares for a stable operation of the PFC pre converter (Figure 16).
Over Voltage 109%
Open Loop 12.5%
PFCVS
PFCGD
-ADC
Notch Filter
PI Loop Control
PWM
Gate Drive
Under Voltage 75%
Over Current 1V 5.0%
PFCCS
Bus Voltage 95%
ZCD Start Up 1.5V / 0.5V
PFCZCD
THD Correction
Int. Reference VPFCVS = 2.5 V
Clock 870 kHz
Figure 16: Structure of the mixed digital and analog control of the PFC pre converter The zero current detection (ZCD) is sensed by the PFCZCD pin via R13 (Figure 3). The information of finished current flow during demagnetization is required in CritCM and in DCM as well. The input is equipped with a special filtering including a blanking of typically 500 ns and a large hysteresis of typically 0.5 V and 1.5 V VPFCZCD (Figure 16).
Datasheet
Page 22 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.4.4 THD Correction via ZCD Signal
An additional feature is the THD correction (Figure 16). In order to optimize the improved THD (especially in the zones A shown in Figure 17 ZCD @ AC Input Voltage), there is a possibility to extend pulse width of the gate signal (blue part of the PFC gate signal in Figure 17) via variable PFC ZCD resistor (see Resistor R13 in Figure 3) in addition to the gate signal controlled by the VPFCVS signal (gray part of the PFC gate signal in Figure 17).
ZCD @ AC Input Voltage ZCD @ DC Input Voltage
Rectified AC Input Voltage
A B A
DC Input Voltage
0
Voltage at 0 ZCD-Winding
PFC Gate Drive Voltage 0
PFC gate signal (gray) controlled by the VPFCVS PFC gate signal (blue) controlled by the ZCD
Figure 17: THD Optimization using adjustable Pulse Width Extension In case of DC input voltage (see DC Input Voltage in Figure 17), the pulse width gate signal is fixed as a combination of the gate signal controlled by the VPFCVS pin (gray) and the additional pulse width signal controlled by the ZCD pin (blue) shown in Figure 17 ZCD @ DC Input Voltage. The PFC current limitation at pin PFCCS interrupts the ON - time of the PFC MOSFET if the voltage drop at the shunt resistors R18 (Figure 3) exceeds the VPFCCS = 1.0 V (Figure 16). This interrupt will restart after the next sufficient signal from ZCD is available (Auto Restart). The first value of the resistor can be calculated by the ratio of the PFC mains choke and ZCD winding the bus voltage and a current of typically 1.5 mA (see equation below). An adjustment of the ZCD resistor causes an optimized THD.
RZCD
N ZCD * VBUS N PFC = 1.5mA
Equation 1: RZCD a good pratical Value
Datasheet
Page 23 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
The relationship between the extended PFC pulse width and the zero crossing detection current is shown in Figure 19.
2.4.5 Optional THD Correction dedicated for DCM Operation
For applications with a wide input voltage range and / or for applications using a wide variation of the power e.g. dimming, the application might work in the DCM (Discontinuous Conduction Mode). In order to minimize the high order harmonics during DCM, the detection of the DCM should be as close as possible at the point of inflection of the PFC drain source voltage shown in Figure 18. This can be realized with an optional damping network (R4, D10 and Q4 from the AUX pin to the ZCD resistor R13.
PFC Drain Source Voltage
DCM Detection CritCM Detection
0 Voltage at PFC 0 ZCD winding with damping
t
t Output current at Pin AUX in DCM 0 PFC Gate Source Voltage t
0
t
Figure 18: Signal Shapes with optional damping of oscillations during DCM operation of PFC
Figure 19: PFC ON Time Extension versus Zero Crossing Current Signal
Figure 20: Optional Circuit for attenuating oscillations during DCM operation of PFC.
Datasheet
Page 24 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.5
Detection of End-of-Life and Rectifier Effect
Two effects are present by End of Life (EOL): lamp over voltage (EOL1) and a rectifier effect (EOL2). After Ignition (see 1 in Figure 21), the lamp voltage breaks down to its run voltage level with decreasing frequency. By reaching the run frequency, the IC enters the Pre Run Mode for 625 ms. During this period, the EOL detection is still disabled. In the subsequent RUN Mode (2 in Figure 21) the detection of EOL1 (lamp over voltage see 3 Figure 21) and EOL2 (rectifier effect see 4 Figure 21) is complete enabled.
Figure 21: End of Life and Rectifier Effect
2.5.1 Detection of End of Life 1 (EOL1) - Lamp Overvoltage
The event of EOL1 is detected by measuring the positive and negative peak level of the lamp voltage via an AC current fed into the LVS pin (Figure 22). This AC current is fed into the LVS pins (LVS1 for single lamp and LVS2 for multi lamp applications) via Network R41, R42, R43 and the low pass filter C40 and R45 see Figure 3. If the sensed AC current exceeds 210 APP for longer than 620 s, the status of end-of-life (EOL1) is detected (lamp overvoltage / overload see Figure 22 LVSAC Current). The EOL1 fault results in a latched power down mode (after trying a single restart) the controller is continuously monitoring the status until EOL1 status changes e.g. a new lamp is inserted.
Figure 22: End of Life (EOL1) Detection, Lamp Voltage versus AC LVS Current Datasheet Page 25 of 56 ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.5.2 Detection of End-of-Life (EOL2) - Rectifier Effect
The rectifier effect (EOL2) is detected by measuring the positive and negative DC level of the lamp voltage via a current fed into the LVS pin (Figure 23). This current is fed into the LVS pins (LVS1 for single lamp and LVS2 for multi lamp applications) via Network R41, R42 and R43 (see Figure 3). If the sensed DC current exceeds 42 A (Figure 23 LVSDC Current) for longer than 2500 ms, the status of end-of-life (EOL2) is detected. The EOL2 fault results in a latched power down mode (after trying a single restart) the controller is continuously monitoring. Only the insert of a new lamp resets the status of the IC.
Figure 23: End of Life (EOL2) Detection, Lamp Voltage versus DC LVS Current
Datasheet
Page 26 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.6
Detection of Capacitive Load
In order to prevent a malfunction in the area of Capacitive Load (see Figure 24) during Run Mode due to certain deviations from the normal load (e.g. harmed lamp, sudden break of the lamp tube ...), the IC has three integrated thresholds - sensed only via the LSCS (pin 1). The controller distinguish between two different states of capacitive load, the detection of working without load (idling detection, CapLoad 1) and working with short over current (CapLoad 2). This state (CapLoad 2) is affecting an operation below the resonance in the capacitive load area (Figure 24). In both cases, the IC results in a latched power down mode after a single restart. After latching the power down mode, the controller is continuously monitoring the status of the fault and restarts after the fault disappears e.g. in case of inserting a new lamp.
Lamp Voltage vs Frequency @ different Modes
1000 900 800 Lamp Voltage [V] 700 600 500 400 300 200 100 0 10000 1000 900
Area of Inductive Load Behavior Area of Capacitive Load Behavior
IGNITION
800 700 600 500 400 300 200
Load
PRE Run and RUN Mode
After IGNITION
100 0 100000
Pre Heating
Frequency [Hz]
After Ignition Before Ignition
Figure 24: Capacitive and Inductive Operation
Datasheet
Page 27 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.6.1 Capacitive Load 1 (Idling Detection - Current Mode Preheating)
A capacitive load 1 operation (idling) is detected when the voltage at the LSCS pin is below + 100 mV during the second 50% ON - time of the low side MOSFET (see Capacitive Load 1 (Idling) in Figure 25). If this status is present for longer than 2500 ms, the controller results a latched power down mode after trying a single restart. The controller is keep monitoring continuously the status until an adequate load is present (e.g. lamp removal), than the IC changes into a normal operation.
Figure 25: Capacitive Mode 1 Operation without load during Run Mode
2.6.2 Capacitive Load 2 (Over Current / Operation below Resonance)
A capacitive load 2 operation is detected if the voltage at the LSCS pin drops below a second threshold of VLSCS = - 100 mV directly before the high side MOSFET is turned on or exceeds a third threshold of VLSCS = 2.0 V during ON switching of the high side MOSFET. If this over current is present for longer than 620 s, the IC results a latched power down mode after trying a single restart. The controller keeps monitoring continuously the status until an adequate load is present e.g. a new lamp is inserted, then the IC changes into a normal operation.
Normal Operation VDSLS IDSLS VGateHS VGateLS VLSCS
+ 2.0 V
Capacitive Load 2 (Over Current) VDSLS IDSLS VGateHS VGateLS VLSCS
+ 2.0 V
- 100 mV
- 100 mV
tCAPLOAD 1
tCAPLOAD 2
tCAPLOAD 2
Figure 26: Capacitive Mode 2 - Operation with Over Current Datasheet Page 28 of 56 ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.6.3 Adjustable self adapting Dead Time
The dead time between the turn OFF and turn ON of the half - bridge drivers is adjustable (C16 see Figure 3) and detected via a second threshold (- 100 mV) of the LSCS voltage. The range of the dead time adjustment is 1.25 s up to 2.5 s during all operating modes. Start of the dead time measurement is the OFF switching of the high side MOSFET. The finish of the dead time measurement is, when VLSCS drops for longer than typical 280ns (internal fixed propagation delay) below -100mV. This time will be stored (stored dead time) and the low side gate driver switches ON. The high side gate driver turns ON again after OFF switching of the low side switch and the stored dead time.
Normal Operation in RUN Mode VDSLS
VLSCS
VLSCS = -100mV END of Dead Time Measurement
Gate LS
Gate HS
START of Dead Time Measurement
Dead Time 280 ns Propagation Delay
Dead Time
Stored Dead Time
Figure 27: Dead Time of ON and OFF of the Half Bridge Drivers
Stored Dead Time
Datasheet
Page 29 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.7
Emergency Lighting
Line interruptions (bus voltage drops) are detected by the PFCVS. If the rated PFC bus voltage drops below VBUSRated < 75 % during run mode, the controller detects a PFC bus under voltage. In order to meets the emergency lighting standards, the controller distinguishes two different states of a PFC bus under voltage, a short and a long term PFC bus under voltage. A timer increases the time as long as a bus under voltage is present. A short term bus under voltage is detected if the timer value stays below t < 800ms typically (500ms min.) after the bus voltage reaches the nominal level again. These causes a restart without preheating (emergency standard of VDE0108) see Figure 28. When the timer exceeds t > 800 ms, the controller forces a complete restart of the system due to a long term bus under voltage (Figure 29).
Datasheet
Page 30 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.7.1 Short Term PFC Bus Under Voltage
A short term PFC bus under voltage (Figure 28) is detected if the duration of the under voltage does not exceed 800 ms (timer stays below t < 800ms see Figure 28). In that case, the PFC and inverter drivers are immediately switched off and the controller is continuously monitoring the status of the bus voltage in a latched power down mode (ICC < 170 A). If the signal at the LVS PIN exceeds 18A and the rated bus voltage is above 12.5% within the timer is below t < 800 ms, the controller restarts from power up without preheating. The timer resets to 0 when entering the Run Mode.
Bus Voltage Drop for t < 800 ms Restart without Preheating VBUSRated
100% 75%
RUN Mode Power Down Mode Pre Run Run Mode Interrupt for t < 800 ms
VCC
16V
ICC
< 6 mA + IQGate Timer
t = 800ms
< 6 mA + IQGate
< 160 A
IPreheating
VLamp
Figure 28: BUS Voltage Drop below 75% (rated Bus Voltage) for t < 800 ms during RUN Mode
Datasheet
Page 31 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.7.2 Long Term PFC Bus Under Voltage
If the duration of the bus under voltage exceeds t > 800ms see Figure 29, the controller forces an under voltage lock out (UVLO). The chip supply voltage drops below VCC = 10.6 V and the chip supply current is below ICC < 130A. When the Vcc voltage exceeds the 10.6V threshold again, the IC current consumption is below ICC < 160A. In that case, the controller resets the timer and restarts with the full start up procedure including Monitoring, Power Up, Start Up, Soft Start, Preheating, Ignition, Pre Run and Run Mode as shown in Figure 29.
Bus Voltage Drop for t > 800 ms Restart with full Start Procedure VBUSRated
95% 75%
RUN Mode Power Down Mode Run Mode Interrupt for t > 800 ms
VCC
16V UVLO @ 10.6V
ICC
< 6 mA + IGate Timer
t = 800ms
< 6 mA + IGate
< 160 A <160 A
IPreheating
VLamp
Figure 29: BUS Voltage Drop below 75% (rated Bus Voltage) for t > 800 ms during RUN Mode
Datasheet
Page 32 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.8
Built in Customer Test Mode Operation
nd
In order to decrease the final ballast testing time for customers, the 2 generation of ballast IC supports an integrated built in Customer Test Mode and several functions to disable some features and states of the IC.
2.8.1 Pre Heating Test Mode
This feature forces the IC to stay in the pre heating mode (see chapter 2.8.1.2) or to starts the ignition immediately without any preheating (see chapter 2.8.1.1 skip pre heating). A resistor at this pin defines the duration of the pre heating phase. Normally, the pre heating phase is in a range of 0ms up to 2500ms set via a resistor RRTPH = 0 up to 25k from the RTPH pin to GND. The pre heating phase is skipped when the RTHP pin is set to GND. If the signal at this pin is VRTPH > 5.0 V, the IC remains in the pre heating mode.
2.8.1.1
Skip the Pre Heating Phase - Set RTPH Pin to GND
The Pre Heating phase can be skipped in set the RTPH pin 11 to GND. Figure 30 shows a standard start up with a set pre heating time via resistor at the RTPH pin 11 to GND (e.g. 8.2 k this is equal to a pre heating phase of app. 820ms). The pre heating phase can be skipped in setting the RTPH pin 11 directly to GND. In that case, the ignition is directly after the soft start phase.
Figure 30: Start UP WITH Pre Heating
Figure 31: Start UP WITHOUT Pre Heating
Datasheet
Page 33 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description 2.8.1.2 IC remains in Pre Heating Phase
This feature gives the customer the flexibility to align the pre heating frequency to the filament power in the pre heating phase. Figure 32 shows a standard start up with the set preheating time of e.g. 820ms with an 8.2 k resistor at the RTPH pin 11. To force the IC remains in pre heating, the voltage level at the RTPH pin 11 has to set to 5.0 V. The duration of this 5.0 V signal defines the time of the pre heating see IPreHeat in figure below.
VCC
17.5 V 16.0 V 14.1 V Chip Supply Voltage
10.6 V
VRTPH UVLO Hysteresis
5.0 V 2.5 V Duration is set by Resistor only
Start Up
Time
IPreHeat Preheating
t = 820 ms when using RRTPH = 8.2kOhm
Time
Time
VLamp
IGNITION Time
Figure 32: Start UP with Pre Heating
Figure 33: Start UP REMAINS in Pre Heating
Datasheet
Page 34 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.8.2 Deactivation of the Filament Detection
In order to deactivate the filament detection of the low or high side filament, set the RES pin 12 or the LVS1 / LVS2 pin 13 / 14 to GND. In that case, the IC starts up into normal operation without checking the filaments e.g. when using an equivalent lamp resistive load instead of a load.
VCC
17.5 V 16.0 V 14.1 V 10.6 V Chip Supply Voltage
VRES
5.0 V 1.6 V 1.3 V
UVLO
Start Up Hysteresis
Time
LVS1 or LVS2 PIN set to GND
VLSGD
10V
VLamp
Figure 34: Deactivation via RES PIN
Figure 35: Deactivation via LVS1 / LVS2 PIN
Figure 34 shows the deactivation of the low and high side filament via set the RES pin 12 to GND. Figure 35 shows the deactivation of the high side filament detection via set the LVS1 or LVS2 pin to GND. Note In case using just one path of a ballast design (single or dual lamp in series) one of the not used LVS pins has to be set to GND.
Datasheet
Page 35 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.8.3 Built in Customer Test Mode (Clock Acceleration)
The built in customer test mode, supported by this IC, saves testing time for customers in terms of ballast end test. In that mode, the IC accelerates the internal clock in order to reduce the time of the 4 different procedures by the following factors (see Table 1). Phase Preheating Time Out Ignition Pre Run Mode EOL2 Duration for Test [ms] 625 118.5 41.7 41.7 Acceleration Factor 4 2 15 60 Nominal Duration [ms] 2500 (max) 237 625 2500
Table 1: Specified Acceleration Factors
2.8.3.1
Enabling of the Clock Acceleration
The clock acceleration (Built in Customer Test Mode) is activated when the chip supply voltage exceeds VCC > 14.1V and the voltages at the Run Frequency and Preheating Frequency pin are set to VRFRUN = VRFPH = 5.0 V ( 5 %) see Figure 35 "Enabling of Clock Acceleration". A RES pin voltage of VRES > 3.5 V up to 5.0 V ( 5 %) prevents a power up of the IC, the IC remains in a mode before powering up. This status is hold as long as the voltage at the RES pin is at VRES > 3.5 V up to 5.0 V ( 5 %) - no power up. Note: after the activation of the clock acceleration mode, the voltage level of 5.0V at the Run Frequency and Preheating Frequency pin (VRFRUN = VRFPH) can be released.
2.8.3.2
Starting the Chip with accelerated Clock
In order to start the IC with an accelerated clock, set the voltage at the RES pin to GND (VRES = 0 V). Figure 36 "Starting the Chip with an accelerated Clock". The IC powers up the system and starts working with an accelerated clock. Now the duration of the different modes are accelerated by Factors shown in Table 1
Figure 36: Clock Acceleration (Built in Customer Test Mode)
Datasheet
Page 36 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
State Diagram
3
3.1
State Diagram
Features during different operating modes
Figure 37: Monitoring Features during different operating Modes
Datasheet
Page 37 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
State Diagram
3.2
Operating Flow of the Start UP Procedure into the Run Mode
Vcc < 10.6V UVLO
Vcc < 10.6V Icc < 130A Vcc > 10.6V
Monitoring
Vcc > 10.6V Icc < 160A Vcc > Vccon(14.1V) & Filament detected VBUS < 12,5% or VBUS > 105%
Power-up
Gate Drives off 14.1V < Vcc Icc approx 6.0mA after 130s & VBUS > 12,5% & VBUS< 105%
See Timing and Handling of Fault Conditions
Start-up
Inverter Gates on PFC Gate on 17.5V> Vcc >10.6V f_Inv = f_START VBUS > 95% within 80ms
See Protection Functions
Fault
17.5V> Vcc >10.6V Icc < 170A Gate Drives off
Softstart
17.5V> Vcc >10.6V f_START=> f_PH after 10ms after 10ms & Flag Skip Preheat & Flag Skip Preheat = Set = Reset // Reset Flag Skip Preheat Preheat & Counter Skip PH // 17.5V> Vcc >10.6V f = f_PH after t_PH= 0...2500ms Time set by R_TPH
Ignition*
Timeout 237ms 17.5V> Vcc >10.6V f_PH => f_RUN f_Inv= f_RUN within t_IGN= 40...237ms
Pre-Run
17,5V> Vcc >10.6V f = f_RUN Reduced Monitoring after t_PRERUN= 625ms
Run
* NOTE: Ignition will reset the Flag Skip Preheating 17.5V> Vcc >10.6V f = f_RUN Complete Monitoring
Figure 38: Operating Flow during Start-up Procedure Datasheet Page 38 of 56 ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
State Diagram
3.3
Auto Restart and Latched Fault Condition Mode
Fault A
Auto Restart Surge; Time OUT Start Up (VBUS < 95% for t > 80 ms)
Fault F
Fault, single Restart Open Filament LS; Inverter Overcurrent; Capacitive Load 1; Capacitive Load 2; Timeout Ignition; EOL 1 (Overload); EOL 2 (Rectifier Effect);
Fault U
BUS Voltage BUS Undervoltage (VBUS < 75% during Run Mode for t > 84s); BUS Overvoltage (VBUS > 109% for t > 625ms);
Increment Fault Counter
INVERTER and PFC Gate OFF Only at Inverter Over current PFC Gate OFF appr. 150s Delayed Power down Icc < 160A Wait 200ms Delay Timer A
NOTE to Set Flag Skip Preheat: When using external Vcc Supply, no reset of Set Flag Skip Preheat. 1st Restart without Preheating while Vcc > UVLO. When LVS deactivated or not from Line.
Set Flag Skip Preheat
Gate drives off Power down Icc < 160A
Wait 100ms Delay Timer A
Fault Counter <2
Y
Increment Counter Skip PH
N
Reset Fault Counter
Y
Counter Skip Preheat >7?
Start Start-up
Wait for Lamp Removal
N
Gate drives off IC remains in active mode
Inverter Gates on PFC Gate on 17.5V> Vcc >10.6V f_Inv = f_START
Lamp removed for min 100ms
Wait for Lamp inserted
Lamp inserted?
NOTE For external Vcc Supply, set Vcc below UVLO.
Lamp Inserted? Or VBUS < 75%
N
N N
t > 80ms? from Power-Up Lamp inserted for min 100ms
Y Wait for UVLO
Y
N
VBUS > 95%?
Y
Fault A Timeout 80ms Start-up
Y
End Start-up
Vcc > 14.1V?
N
Reset Flag Skip Preheat & Counter Skip PH
Vcc < 10.6V?
N
Y Power-up
Gate Drives off
Note: Fault Counter reset after 40s in Run Mode Reset of Flag Skip Preheat after Ignition
Y UVLO
Reset all Latches
Figure 39: Operating Process during Start-up Mode and Handling of Fault Conditions
Datasheet
Page 39 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
4
Protection Functions Matrix
Characteristics of fault Name of Fault Operating Mode Detection is active Power-up 130s Start-up until VBUS > 95% Softstart 10ms Preheat Mode 0 - 2500ms Ignition Mode 40 - 237ms Pre-Run Mode 625ms Consequence
Description of Fault
Type of fault
Monitoring
Supply voltage Vcc < 14.1V before power up Supply voltage Vcc < 10.6V after power up Current into LVS1 pin < 18A before power up Current into LVS2 pin < 18A before power up Voltage at RES pin > 1.6V before power up Voltage at RES pin > 3.2V Bus voltage < 12.5% of rated level 10s after power up Bus voltage < 12.5% of rated level Bus voltage < 12.5% of rated level Bus voltage < 75% of rated level add. shut down delay 120s Bus voltage < 95% of rated level during start-up Bus voltage > 105% of rated level 10s after power up Bus voltage > 109% of rated level in active operation Bus voltage > 109% of rated level in active operation +/- peak level of lamp voltage at Pin LVS above threshold DC level of lamp voltage above +/- threshold Capacitive Load 1
Below startup threshold Below UVLO threshold open filament HS open filament HS open filament LS open filament LS Open Loop detection Open Loop detection Shut down option Undervoltage
S S S S S F S N U U
1s 5s 100s 100s 100s 620s 1s 1s 625ms 84s
Run Mode Prevents power up X Power down, Reset failure latch Prevents power up Prevents power up Prevents power up X Power down,latched Fault Mode, 1 Restart
Keep Gate drives off, restart after Vcc hysteresis
Minimum Duration of effect
X X X X X X X X X X X
X X X X X X X X X
Timeout max A 80ms X start-up time Keep Gate drives off, reOverS 5s X start after Vcc hysteresis voltage Stops PFC FET until PFC N 5s X X X X X X VBUS< 105% Overvoltage Power down, restart Inverter U 625ms X when VBUS<105% Overvoltage Power down,latched EOL 1 F 620s X Fault Mode, 1 Restart Overvoltage Power down,latched EOL 2 F 2500ms X Fault Mode, 1 Restart Rect. Effect Power down,latched Cap Load 1 F 2500ms X Fault Mode, 1 Restart Idling Power down,latched Capacitive Load 2, Cap.Load 2 F 620s X Fault Mode, 1 Restart operation below resonance Overload Run frequency cannot be Timeout F 237ms Power down,latched X achieved Ignition Fault Mode, 1 Restart Stops on-time of PFC Voltage at PFCCS pin > 1.0V PFC N 200ns X X X X X X FET immediately Overcurrent Voltage at LSCS pin > 0.8V Inverter N 200ns Activates X current lim Ignition control Power down,latched Voltage at LSCS pin > 0.8V Inverter F 500ns X X Fault Mode, 1 Restart overcurrent Power down,latched Voltage at LSCS pin > 1.6V Inverter F 500ns X X X X Fault Mode, 1 Restart overcurrent Power down, restart Voltage at LSCS pin > 0.8V Inverter A 500ns X X when VBUS<109% & VBUS > 109% (Surge) overcurrent After jump into latched fault mode F wait 200ms A single restart attempt after delay of internal timer Reset of failure latch in run mode after 40s Reset of failure latch by UVLO or 40s in run mode S = Start-up condition, N = No Fault, A = Auto-Restart , U = Undervoltage F = Fault with a single Restart, a second F leads to a latched fault / Note: all values @ typical 50 Hz mains frequency
Stops PFC FET until VBUS > 12.5% Power down, restart when VBUS> 12.5% Power down, 100ms delay, restart, skip preheating max 7 times Power down, 200ms delay, restart
Datasheet
Page 40 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5
Electrical Characteristics
Note: All voltages without the high side signals are measured with respect to ground (pin 4). The high side voltages are measured with respect to pin17. The voltage levels are valid if other ratings are not violated.
Absolute Maximum Ratings
5.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 3 (VCC) and pin 18 (HSVCC) is discharged before assembling the application circuit.
Parameter
LSCS Voltage LSCS Current LSGD Voltage LSGD Peak Source Current LSGD Peak Sink Current VCC Voltage VCC Zener Clamp Current PFCGD Voltage PFCGD Peak Source Current PFCGD Peak Sink Current PFCCS Voltage PFCCS Current PFCZCD Voltage PFCZCD Current PFCVS Voltage RFRUN Voltage RFPH Voltage RTPH Voltage RES Voltage LVS1 Voltage LVS1 Current1 LVS1 Current2 LVS2 Voltage LVS2 Current1 LVS2 Current2
Symbol
VLSCS ILSCS VLSGD ILSGDsomax ILSGDsimax VVCC IVCCzener VPFCGD IPFCGDsomax IPFCGDsimax VPFCCS IPFCCS VPFCZCD IPFCZCD VPFCVS VRFRUN VRFPH VRTPH VRES VLVS1 ILVS1_1 ILVS1_2 VLVS2 ILVS2_1 ILVS2_2
Limit Values
min. -5 -3 - 0.3 - 75 - 50 - 0.3 -5 - 0.3 - 150 - 100 -5 -3 -3 -5 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 -6 -1 -3 -6 -1 -3 max. 6 3 Vcc+0.3 5 400 18.0 5 Vcc+0.3 5 700 6 3 6 5 5.3 5.3 5.3 5.3 5.3 7 1 3 7 1 3
Unit
V mA V mA mA V mA V mA mA V mA V mA V V V V V V mA mA V mA mA
Remarks
Internally clamped to 11V
< 500ns < 100ns IC in Power Down Mode < 500ns < 100ns
IC in Power Down Mode IC in active Mode IC in Power Down Mode IC in active Mode
Datasheet
Page 41 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Absolute Maximum Ratings
Parameter
AUX Voltage HSGND Voltage HSGND Voltage Transient HSVCC Voltage HSGD Voltage HSGD Peak Source Current HSGD Peak Sink Current Junction Temperature Storage Temperature Maximum Power Dissipation Thermal Resistance (2 Chips) Thermal Resistance (HS Chip) Thermal Resistance (LS Chip) Soldering Temperature ESD Capability Creepage Distance HS vs. LS VESD
Symbol
VAUX VHSGND dVHSGND /dt VHSVCC VHSGD IHSGDsomax IHSGDsimax TJ TS PTOT RthJA RthJAHS RthJALS
Limit Values
min. - 0.3 - 900 - 40 - 0.3 - 0.3 - 75 0 - 25 - 55 max. 5.3 900 40 18.0 VHSVCC+0.3 0 400 150 150 2 60 120 120 260 2 2.0 2.43
Unit
V V V/ns V V mA mA C C W K/W K/W K/W C kV mm
Remarks
Referring to GND Referring to HSGND Internally clamped to 11V < 500ns < 100ns
-- -- -- -- -- --
1.9
PG_DSO-19-1 Tamb=25C PG_DSO-19-1 PG_DSO-19-1 PG_DSO-19-1 Wave Soldoldering1) Human Body Model2)
Rated Bus Voltage (95%)
1) 2)
VPFCVS95
2.33
V
According to JESD22A111 According to EIA/JESD22-A114-B (discharging an 100 pF Capacitor through an 1.5k series Resistor)
Datasheet
Page 42 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Operating Range
5.2
Operating Range
Parameter Symbol
VHSVCC VHSGND VVCC
Limit Values
min. Max. 17.5 900 17.5 VHSVCCOff - 900 VVCCOff
Unit
V V V
Remarks
Referring to HSGND Referring to GND
HSVCC Supply Voltage HSGND Voltage VCC Voltage @ 25C
TJ = 25C TJ = 125C
In active Mode In active Mode
VCC Voltage @ 125C
LSCS Voltage Range PFCVS Voltage Range PFCCS Voltage Range
VVCC
VLSCS VPFCVS VPFCCS
VVCCOff
-4 0 -4
18.0
5 4 5
V
V V V
PFZCD Current Range
LVS1, LVS2 Voltage Range LVS1, LVS2 Current Range LVS1, LVS2 Current Range RFPH Frequency RFPH Source Current Range
IPFCZCD VLVS1,LVS2
ILVS1,LVS2 ILVS1,LVS2
-3 -6
2)
3 6
1)
mA V
A mA
In active Mode
IC Power Down Mode IC active Mode
210 2.5
- 2.5
FRFPHrange IRFPH VRTPH
Tj FRFPH FRFRUN tRTPH RRFRUN RRFPH RRTPH fMains
FRUN - 500 0
- 25 FRFRUN 20 0 4 4 0 45
150 0 2.5
125 150 120 2500 25
kHz A V
C kHz kHz ms k k k Hz NOTCH Filter Operation RRFRUN parallel to RRFPH Range set by RFPH Range set by RFRUN Range set by RTPH
@ VRFPH = 2.5V
RTPH Voltage Range
Junction Temperature Adjustable Preheating Freq. Adjustable Run Frequency Adjustable Preheating Time Set Resistor for Run Feq. Set Resistor for Preheat Feq. Set Resistor for Preheat Time Mains Frequency
1) 2)
--
25 65
Limited by Maximum of Current Range at LVS1, LVS2 Limited by Minimum of Voltage Range at LVS1, LVS2
Datasheet
Page 43 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3
Characteristics
5.3.1 Power Supply Section
Note: The electrical Characteristics involve the spread of values given within the specified supply voltage and junction temperature range TJ from -25 C to 125 C. Typical values represent the median values, which are related to 25 C. If not otherwise stated, a supply voltage of 15V and VHSVCC = 15V is assumed and the IC operates in active mode. Furthermore, all voltages are referring to GND if not otherwise mentioned.
Parameter VCC Quiescent Current1 VCC Quiescent Current2 VCC Supply Current VCC Supply Current in Latched Fault Mode LSVCC Turn-On Threshold LSVCC Turn-Off Threshold LSVCC Turn-On/Off Hyst. VCC Zener Clamp Voltage VCC Zener Clamp Current High Side Leakage Current HSVCC Quiescent Current HSVCC Quiescent Current HSVCC Turn-On Threshold HSVCC Turn-Off Threshold HSVCC Turn-On/Off Hyst. Low Side Ground
1) 2)
Symbol IVCCqu1 IVCCqu2 IVCCSupply IVCCLatch VVCCOn VVCCOff VVCCHys VVCCClamp IVCCZener IHSGNDleak
1) IHSVCCqu1 1) IHSVCCqu2 1) VHSVCCOn 1) VHSVCCOff 1) VHSVCCHy
Limit Values min. -- -- -- -- 13.6 10.0 3.2 15.5 2.5 -- -- 0.3 9.6 7.9 1.4 typ. 90 120 4.2 110 14.1 10.6 3.6 16.3 -- 0.01 170 0.65 10.1 8.4 1.7 max. 130 160 6.0 170 14.6 11.0 4.0 16.9 5 2 250 1.2 10.7 9.1 2.0
Unit A A mA A V V V V mA A A mA V V V
Test Condition VVCC = VVCCOff - 0.5V VVCC = VVCCOn - 0.5V VPFCVS > 2.725V VRES = 5V
2)
Hysteresis IVCC = 2mA/VRES = 5V VVCC = 17.5V/VRES = 5V VHSGND = 800V, VGND=0V VHSVCC = VHSVCCOn - 0.5V VHSVCC > VHSVCCOn
2)
Hysteresis
GND
Referring to High Side Ground (HSGND) With inactive Gate
Datasheet
Page 44 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3.2 PFC Section
5.3.2.1
Parameter Turn - Off Threshold Over Current Blanking + 1) Propagation Delay Leading Edge Blanking PFCCS Bias Current 1) Propagation Delay = 50ns
PFC Current Sense (PFCCS)
Symbol VPFCCSOff tPFCCSOff tBlanking IPFCCSBias Limit Values min. 0.95 140 180 - 0.5 typ. 1.0 200 250 -- max. 1.05 260 310 0.5 Unit V ns ns A Pulse Width when VPFCCS > 1.0V VPFCCS = 1.5V Test Condition
5.3.2.2
Parameter
PFC Zero Current Detection (PFCZCD)
Symbol
1) 2)
Limit Values min. 1.4 0.4 -- 4.1 - 1.7 - 0.5 - 0.5 350 500 typ. 1.5 0.5 1.0 4.6 - 1.4 -- -- 500 700 max. 1.6 0.6 -- 5.1 - 1.0 5.0 0.5 650 900
Unit V V V V V A A ns pAxs
Test Condition
Zero Crossing upper Thr. Zero Crossing lower Thr. Zero Crossing Hysteresis
VPFCZCDUp VPFCZCDLow VPFCZCDHys VPFCZCDpclp VPFCZCDnclp IPFCZCDBias IPFCZCDBias tRingsup
t
Clamping of pos. Voltages Clamping of neg. Voltages PFCZCD Bias Current PFCZCD Bias Current PFCZCD Ringing Su. Time Limit Value for ON Time Extension
1) 2)
IPFCZCDSink = 2mA IPFCZCDSource = - 2mA VPFCZCD = 1.5V VPFCZCD = 0.5V
3)
x IZCD
Turn OFF Threshold Turn ON Threshold 3) Ringing Suppression Time
5.3.2.3
Parameter
PFC Bus Voltage Sense (PFCVS)
Symbol VPFCVSRef VPFCVSRUp VPFCVSLow VPFCVSHys VPFCVSUV VPFCVSUV VPFCVS95 IPFCVSBias Limit Values min. 2.47 2.68 2.57 70 1.835 0.237 2.325 - 1.0 Typ. 2.50
2.73 2.63
max. 2.53 2.78 2.68 130
1.915 0.387 2.425
Unit V V V mV V V V A
Test Condition 1.2 %
Trimmed Reference Voltage Overvoltage turn Off (109%) Overvoltage turn On (105%) Overvoltage Hysteresis Under voltage (75%) Under voltage (12.5%) Rated Bus Voltage (95%) PFCVS Bias Current
100
1.88 0.31 2.38
4 % rated Bus Voltage
--
1.0
VPFCVS = 2.5V
Datasheet
Page 45 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics 5.3.2.4
Parameter Initial ON - Time
1) 2)
PFC PWM Generation
Symbol tPFCON_initial tPFCON_max tPFCON_min tPFCRep tPFCOff Limit Values min. -- 18 160 47 42 Typ. 4.0 22.7 270
52 47
max. -- 26 370 57 52
Unit s s ns s s
Test Condition VPFCZCD = 0V 0.45V < VPFCVS < 2.45V
Max. ON - Time Switch Threshold from CritCM into DCM 1) Repetition Time Off Time
1) 2)
VPFCZCD = 0V
When missing Zero Crossing Signal At the Maxima of the AC Line Input Voltage
5.3.2.5
Parameter
PFC Gate Drive (PFCGD)
Symbol Limit Values min. 0.4 0.4 - 0.2 10.0 Typ. 0.7 0.75 0.3 11.0 -- -- 0.75 1.0 - 100 500
11.7 220 45
max. 0.9 1.1 0.6 11.6 -- -- 1.1 1.5 -- -- 12.3 380 70
Unit V V V V V V V V mA mA V ns ns
Test Condition IPFCGD = 5mA IPFCGD = 20mA IPFCGD = -20mA IPFCGD = -20mA IPFCGD = -1mA / VVCC IPFCGD = -5mA / VVCC
1) 1)
PFCGD Low Voltage
VPFCGDLow
PFCGD High Voltage PFCGD active Shut Down PFCGD UVLO Shut Down
PFCGD Peak Source Current PFCGD Peak Sink Current PFCGD Voltage during sink Current
VPFCGDHigh VPFCGASD VPFCGDuvlo IPFCGDSouce IPFCGDSink VPFCGDHigh VPFCGDRise VPFCGDFall
9.0 8.5 0.4 0.3 -- -- 11.0 80 20
IPFCGD = 20mA VVCC=5V IPFCGD = 5mA VVCC=2V
2) + 3) 2) + 3)
IPFCGDSinkH = 3mA 2V > VLSGD > 8V 8V > VLSGD > 2V
2) 2)
PFC Rise Time PFC Fall Time
1) 2)
VVCC = VVCCOff + 0.3V RLoad = 4 and CLoad = 3.3nF 3) The Parameter is not Subject to Production Test - verified by Design / Characterization
5.3.2.6
Parameter
Auxiliary (AUX)
Symbol VAUXOff VAUXOn1 VAUXOn2 IAUX Limit Values min. -- 1.7 1.8 - 0.60 typ. -- 2.6 2.6 -0.45 max. 0.24 3.1 3.1 - 0.3 Unit V V V mA Test Condition IAUX = 1mA Ip = 0A
1) 1)
AUX Voltage OFF Level AUX Voltage ON Level 1 AUX Voltage ON Level 2 AUX Current
1)
Ip = 1mA VAUX = 1V / IP = 0A
IP = the positive Current into PIN ZCD Page 46 of 56 ICB2FL01G V1.2
Datasheet
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3.3 Inverter Section
5.3.3.1
Parameter
Overcurrent Shut Down Volt. Overcurrent Shut Down Volt.
Low Side Current Sense (LSCS)
Symbol VLSCSOvC1 VLSCSOvC2 tLSCSOvC VLSCSCap1 tLSCSCap1 VLSCSCap2 tLSCSCap2 VLSCSCap3 tLSCSCap3 ILSCSBias Limit Values min. 1.5 0.75 450 80 -- 1.8 -- - 120 -- -1.0 typ. 1.6 0.8 600 100 280 2.0 50 - 100 280 -- max. 1.7 0.85 700 123 -- 2.2 -- - 77 -- 1.0 Unit V V ns mV ns V ns mV ns A
5) 1) 2)
Test Condition
Duration of Overcurrent
Capacitive Mode Det. Level 1 Capacitive Mode Duration 1 Capacitive Mode Det. Level 2 Capacitive Mode Duration 2 Capacitive Mode Det. Level 3 Capacitive Mode Duration 3
During Run Mode
3)
During Run Mode
4)
LSCS Bias Current
1) 2)
@ VLSCS = 1.5V
Overcurrent Voltage Threshold active during: Start Up, Soft start, Ignition and Pre Run Mode Overcurrent Voltage Threshold active during: Preheating and Run Mode 3) Active during 2nd 50% Duty Cycle of LSGD in Run Mode 4) Active during Turn ON of the HSGD in Run Mode 5) Active before Turn ON of the HSGD in Run Mode
Datasheet
Page 47 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics 5.3.3.2
Parameter
Low Side Gate Drive (LSGD)
Symbol Limit Values min. 0.4 0.4 - 0.3 10.0 typ. 0.7 0.8 0.2 10.8 -- -- 0.75 1.0 - 50 300
11.7
max. 1.0 1.2 0.5 11.6 -- -- 1.1 1.5 -- -- -- 380 60
Unit V V V V V V V V mA mA V ns ns
Test Condition ILSGD = 5mA ILSGD 1)
2) 3) 5) 5)
LSGD Low Voltage
VLSGDLow
ILSGD = 20mA
= - 20mA (Source)
LSGD High Voltage LSGD active Shut Down LSGD UVLO Shut Down LSGD Peak Source Current LSGD Peak Sink Current
LSGD Voltage during 5)
VLSGDHigh VLSGDASD VLSGDUVLO ILSGDSource ILSGDSink VLSGDHigh tLSGDRise tLSGDFall
9.0 8.5 0.4 0.3 -- -- -- 80 20
VCC=5V / ILSGD = 20mA VCC=2V / ILSGD = 5mA
4) + 6) 4) + 6)
5)
5)
ILSGDsinkH = 3mA 2V < VLSGD < 8V 8V > VLSGD > 2V
4) 4)
LSGD Rise Time LSGD Fall Time
1) 2)
220 35
ILSGD = - 20mA Source Current VCCOFF + 0.3V and ILSGD = - 1mA Source Current 3) VCCOFF + 0.3V and ILSGD = - 5mA Source Current 4) Load: RLoad = 10 and CLoad = 1nF 5) Sink Current 6) The Parameter is not Subject to Production Test - verified by Design / Characterization
Datasheet
Page 48 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics 5.3.3.3
Parameter Fixed Start - Up Frequency Duration of Soft Start
RFRUN Voltage in Run Mode
Inverter Control Run (RFRUN)
Symbol FStartUp tSoftStart VRFRUN FRFRUN FRFRUN1 FRFRUN2 FRFRUN3 IRFRUNmax Limit Values min. 121.5 9 -- 49 -- -- -- -- typ. 135 11 2.5 50 20 40 100 -1000 max.
148.5
Unit kHz ms V kHz kHz kHz kHz A
1)
Test Condition
13.5 -- 51 -- -- -- - 650
@ 100ARun Frequency Adjustable Run Frequency
RFRUN max. Current Range
1)
Shift Start Up Frequency to Preheating Frequency
5.3.3.4
Parameter
Inverter Control Preheating (RFPH, RTPH)
Symbol VRFPH FRFPH1 IRFPHmax IRTPH tRTPH1 tRTPH2 Limit Values min. -- 97 -- -- 950 50 -- -- -- typ. 2.5 100 -1000 - 100 1000 100 500 2000 2500 max. -- 103 - 550 -- 1050 150 -- -- -- Unit V kHz A A ms ms ms ms ms RRTPH1 = 10k RRTPH2 = 1k RRTPH3 = 5k RRTPH4 = 20k RRTPH5 = 25k Test Condition VRFPH = 0V in Run Mode RRFPH = RRFRUN = 10k @ VRFPH = 0V
RFPH Voltage Preheating Preheating Frequency
RFPH max. Current Range Current for set Preh. Time
Preheating Time
tRTPH3 tRTPH4 tRTPH5
Datasheet
Page 49 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics 5.3.3.5
Parameter
Restart after Lamp Removal (RES)
Symbol VRES1 Limit Values min. 1.55 1.25 --
- 53.2
typ. 1.60 1.30 3.2 -42.6 -35.4 -21.3 -17.7
max. 1.65 1.35 --
-32.0
Unit V V V A A A A
Test Condition UVLO, VCC < VCCON Run Mode VRES = 1V ; LVS1 = 5A VRES = 2V ; LVS1 = 5A VRES = 1V ; LVS1 = 30A VRES = 2V ; LVS1 = 30A
High Side Filament In Det.
VRES2 VRES3 IRES1
RES Current Source
IRES2 IRES3 IRES4
-44.2
- 26.6
-26.6
- 16.0
- 22.1
-13.3
5.3.3.6
Parameter
Lamp Voltage Sense (LVS1, LVS2)
Symbol ILVSSource VLVSEnable1 ILVSSink VLVSClamp ILVSSourceAC ILVSDCPos ILVSDCNeg Limit Values min. - 5.0 350 8.0 --
190 34 - 50
typ. - 3.0 530 12.0 6.5 210 42 - 42
max. - 2.0 750 18.0 --
230 50 - 34
Unit A mV A V App A A
Test Condition VLVS = 0V
1)
Source Current before Startup
Enable Lamp Monitoring Sink Current for Lamp Det. Positive Clamping Voltage AC EOLCurrent Threshold Positive EOL Current Thr. Negative EOL Current Thr.
1)
VLVS > VLVSClamp @ ILVS = 300A ILVS > ILVSEOLpp EOL 1 ILVS > ILVSDCPos EOL 2 ILVS > ILVSDCNeg EOL 2
If VLVS < VLVS1Enable1 Monitoring is disabled
Datasheet
Page 50 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
5.3.3.7
Parameter
High Side Gate Drive (HSGD)
Symbol Limit Values Min. 0.02 0.5 - 0.4 9.7 7.8 0.05 -- -- 140 20 typ. 0.05 1.1 - 0.2 10.5 -- 0.22 - 50 300 220 35 max. 0.1 2.5
- 0.05
Unit V V V V V V mA mA ns ns
Test Condition IHSGD = 5mA (sink) IHSGD = 100mA (sink) ILSGD = - 20mA (source) VCCHS=15V IHSGD = - 20mA (source) VCCHSOFF + 0.3V IHSGD = - 1mA (source) VCCHS=5V IHSGD = 20mA (sink) RLoad = 10+CLoad = 1nF 1)
RLoad = 10+CLoad = 1nF 1) RLoad = 10+CLoad = 1nF RLoad = 10+CLoad = 1nF
HSGD Low Voltage
VHSGDLow
HSGD High Voltage HSGD active Shut Down HSGD Peak Source Current HSGD Peak Sink Current HSGD Rise Time HSGD Fall Time
1)
VHSGDHigh VHSGDASD IHSGDSource IHSGDSink THSGDRise THSGDFall
11.2 -- 0.5 -- -- 300 70
2V < VLSGD < 8V 8V > VLSGD > 2V
The Parameter is not Subject to Production Test - verified by Design / Characterization
5.3.3.8
Delay Timer 1 Delay Timer 2
Timer Section
tTIMER1 tTIMER2 tInv tDeadMax tDeadMin tDeadMax tDeadMin tIgnition tNOIgnition tPRERUN 70 74 100 2.25 1.0 - 200 - 200 34 197 565 100 84 130 2.5 1.25 -- -- 40 -- 625 160 94 160 2.75 1.5 200 200 48 236 685 ms ms s s s ns ns ms ms ms
For Lamp Detection
For VBUS > 95%
Inverter Time Inverter Dead Time Max Inverter Dead Time Min Inverter Dead Time Max Inverter Dead Time Min Min. Duration of Ignition Max. Duration of Ignition Duration of Pre - Run
5.3.3.9
Voltage at RTPH Pin Voltage at RTPH Pin
Built in Customer Test Mode
VRTPH VRTPH VLVS1,2 VRES VRFPH VRFRUN VCC VRES 0 5.0 0 0 5.0 5.0 > 14.1 0 V V V V V
1)
Preheating Time = 0ms (Skipped Preheating)
Voltage at LVS1 / LVS2 Pin Voltage at RES Pin Voltage at RFPH Pin Voltage at RFRUN Pin Voltage at VCC Pin Voltage at RES Pin
IC remains in Preheating Disables Lamp Voltage Sense Disable the Filament Detection Built in Customer Test Mode - Clock Acceleration. Decreasing Time for the following Procedures. Preheating by Factor 4 Timeout Ignition by Factor 2 Pre RUN by Factor 15 EOL by 60
V
1) 1)
V V
1) Tolerance for this voltage is: 5%
Datasheet
Page 51 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Application Example
6
6.1
Application Example
Schematic Ballast 54W T5 Single Lamp
Figure 40: Application Circuit of Ballast for single Fluorescent Lamp Voltage Mode Preheating
Datasheet
Page 52 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Application Example
6.2
Bill of Material
090402-1-L-54W-T5-FL2-VM 54W T5, single Lamp, Voltage Mode Preheat Input Voltage 180VAC...270V AC
Package
BOM
ICB2FL01G
V_BUS= 412V R1 R2 R3 R4 R402 R403 R11 R12 R13 R14 R15 R16 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R30 R34 R35 R36 R36A R61 470k 470k not assembled not assembled not assembled not assembled 470k 470k 33k 820k 820k 22 1 not assembled 10k 11k (45,5kHz!) 8,2k (106,4kHz!) 10k (1000ms!) 0,68 0,68 ( 0,34) 22 22 33 150k 150k 56k 0 0 Package .1206 .1206 .1206 .1206 .1206 .1206 .1206 .1206 .1206 .1206 .1206 .0805 .1206 .1206 .0805 .0805 .0805 .0805 .1206 .1206 .1206 .0805 .1206 .1206 .1206 .1206 .1206 .1206 Gen-2
F1 K1/1 K1/2 K1/3 K2/1 K2/2 K2/3 K3/1 K3/2 K3/3 IC1 Q1 Q2 Q3 Q4 D1...4 D5 D6 D7 D8 D9 D10 D11 DR12 D13 D61 L101 L1 PFC L2 L 21 L 22 L 23 C1 C2 C3 C4 C5 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C40
Fuse 1A fast Fuse Holder AC Input AC Input PE not connected High Side Filament High Side Filament Low Side Filament Low Side Filament not connected ICB2FL01G SPD03N60C3 SPD03N60C3 SPD03N60C3 not assembled S1M MURS160T3 BYG26J BYG22D BYG22D BZX284C16 not assembled not assembled 110k not assembled not assembled 2x68mH/0,6A 1,58mH total gap= 1.1mm 1,46mH total gap= 2mm 100H 100H not assembled 220nF/X2/305V 33nF/630V/MKT 3,3nF/Y2-RM10 220nF/X2/305V not assembled 10F/450V 2,2nF/50V 100nF/50V 1F/63V/MKT 68nF/50V 33nF/630V/MKT 1nF/630V/MKT 100nF/630V not assembled 22nF/50V 4,7nF/1600V/MKP 22nF/400V/MKT 22nF/400V/MKT not assembled not assembled not assembled 220nF/25V
Wickmann
Typ 370
B-Nr: 250-203
B-Nr: 250-203
B-Nr: 250-203 Infineon Infineon Infineon Infineon Infineon Fairchild ON Semi Philips Philips Philips Philips >GE834 SO-20 D-Pack D-Pack D-Pack SOT-223
DO-214AC
(1000V/1A/2s) (600V/1A/75ns) (600V/1A/30ns) (200V/1A/25ns) (200V/1A/25ns)
SMB SOD124 DO214 DO214 SOD110
SOD110 B82732F2601B001 105turns/10turns EFD25/13/9 B78326P7373A005 T1904 EFD25/13/9 182turns B78326P7374A005 T1905 B82144B1104J000 RM5 B82144B1104J000 RM5 B82144B1104J000 RM5 B32922C3224M000 RM15 B32521N8333K000 RM10 B32021A3332 RM10/15 B32922C3224M000 RM15 B32529C8102K000 RM5 B43888A5106M000 single ended .0805 .0805 Epcos B32529C0105K000 RM5 Epcos .0805 Epcos B32521N8333K000 RM10 Epcos B32529C8102K000 RM5 Epcos B32612A6104K008 RM15 RM7,5 .0805 Epcos B32612-J1472J008 RM15 Epcos B32620A4223J000 RM7,5/10 Epcos B32620A4223J000 RM7,5/10 Epcos B32620A4223J000 RM7,5/10 Epcos B32612-J1472J008 RM15 Roederstein RM7,5 .0805
Philips Epcos Epcos 2 pcs Epcos 2 pcs Epcos Epcos Epcos Epcos Epcos Epcos Epcos Epcos Epcos
connect LVS2 (pin14) to GND R41 R42 R43 R44 R45 68k 68k 68k 68k 6,8k .1206 .1206 .1206 .1206 .1206
R61
0
.0805
EOL1 threshold 167Vpeak x 1.5=250V peak 5W
Datasheet
Page 53 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Application Example
6.3
Multi Lamp Ballast Topologies
Figure 41: Parallel 2 Lamp Ballast Circuit with Current Mode Preheating
Figure 42: Serial 2 Lamp Ballast Circuit with Voltage Mode Preheating
Datasheet
Page 54 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Figure 43: 4 Lamp Ballast Circuit with Voltage Mode Preheating
Datasheet
Page 55 of 56
ICB2FL01G V1.2
2nd Generation FL-Controller for FL-Ballasts
Application Example
7
Package Outlines
Figure 44: Package Outline with Creepage Distance
Datasheet
Page 56 of 56
ICB2FL01G V1.2

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